Reliability Wearout Mechanisms in Advanced CMOS Technologies - (IEEE Press Microelectronic Systems) (Hardcover)
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<p/><br></br><p><b> Book Synopsis </b></p></br></br>This invaluable resource tells the complete story of failure mechanisms--from basic concepts to the tools necessary to conduct reliability tests and analyze the results. Both a text and a reference work for this important area of semiconductor technology, it assumes no reliability education or experience. It also offers the first reference book with all relevant physics, equations, and step-by-step procedures for CMOS technology reliability in one place. Practical appendices provide basic experimental procedures that include experiment design, performing stressing in the laboratory, data analysis, reliability projections, and interpreting projections.<p/><br></br><p><b> From the Back Cover </b></p></br></br><b>A comprehensive treatment of all aspects of CMOS reliability wearout mechanisms</b> <p>This book covers everything students and professionals need to know about CMOS reliability wearout mechanisms, from basic concepts to the tools necessary to conduct reliability tests and analyze the results. It is the first book of its kind to bring together the pertinent physics, equations, and procedures for CMOS technology reliability in one place. Divided into six relatively independent topics, the book covers: </p> <ul> <li> <p>Introduction to Reliability</p> </li> <li> <p>Gate Dielectric Reliability</p> </li> <li> <p>Negative Bias Temperature Instability</p> </li> <li> <p>Hot Carrier Injection</p> </li> <li> <p>Electromigration Reliability</p> </li> <li> <p>Stress Voiding</p> </li> </ul> <p>Chapters conclude with practical appendices that provide very basic experimental procedures for readers who are conducting reliability experiments for the first time. <i>Reliability Wearout Mechanisms in Advanced CMOS Technologies</i> is ideal for students and new engineers who are looking to gain a working understanding of CMOS technology reliability. It is also suitable as a professional reference for experienced circuit design engineers, device design engineers, and process engineers.</p><p/><br></br><p><b> About the Author </b></p></br></br><b>ALVIN W. STRONG, PhD</b>, is retired from IBM in Essex Junction, Vermont. He holds nineteen patents, has authored or coauthored a number of papers, and is a member of the IEEE and chair of the JEDEC 14.2 standards subcommittee. <p><b>ERNEST Y. WU, PhD</b>, is a Senior Technical Staff Member at Semiconductor Research and Development Center (SRDC) in the IBM System and Technology Group. He has authored or coauthored more than 100 technical or conference papers. His research interests include dielectric/device reliability and electronic physics.</p> <p><b>ROLF-PETER VOLLERTSEN, PhD</b>, is a Principal for Reliability Methodology at Infineon Technologies AG in Munich, Germany, where he is responsible for methods and test structures for fast Wafer Level Reliability monitoring and the implementation of fast WLR methods.</p> <p><b>JORDI SUNE, PhD</b>, is Professor of Electronics Engineering at the Universitat Aut¿noma de Barcelona, Spain. He is Senior Member of the IEEE and has coauthored over 150 publications on oxide reliability and electron devices. His research interests are in gate oxide physics, reliability statistics, and modeling of nanometer-scale electron devices.</p> <p><b>GIUSEPPE LaROSA, PhD</b>, is Project Leader of the FEOL technology reliability qualification activities for the development of advanced SOI Logic and eDRAM technologies at IBM, where he is responsible for the implementation and development of state-of-the-art NBTI stress and test methodologies.</p> <p><b>TIMOTHY D. SULLIVAN, PhD</b>, is Team Leader for metallization reliability at IBM's Essex Junction facility. The author of numerous technical papers and tutorials, he holds thirteen patents with several more pending.</p> <p><b>STEWART E. RAUCH, III, PhD</b>, is currently a Senior Technical Staff Member at the IBM SRDC in New York, where he specializes in hot carrier and NBTI reliability of state-of-the-art CMOS devices. He is the author of numerous technical papers and tutorials and holds five patents.</p>
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