Constraining Designs for Synthesis and Timing Analysis - by Sridhar Gangadharan & Sanjay Churiwala (Hardcover)
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<p/><br></br><p><b> About the Book </b></p></br></br><p>This guide to timing constraints in integrated circuit design shows how to maximize performance of IC designs by specifying timing requirements correctly. Coverage includes such design aspects as synthesis, static timing analysis and placement and routing.</p><p/><br></br><p><b> Book Synopsis </b></p></br></br>This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.<p/><br></br><p><b> From the Back Cover </b></p></br></br><p>This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.</p><p> - Provides a hands-on guide to synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints;</p><p>- Includes key topics of interest to a synthesis, static timing analysis or place and route engineer;</p><p>- Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing;</p><p>- Explains fundamental concepts and provides exact command syntax.</p><p/><br></br><p><b> About the Author </b></p></br></br><p>Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx. </p><p>Sridhar Gangadharan is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA. </p>
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